1. Field of the Invention
The present invention relates to a communication apparatus suitable for mobile communications use, and a transmit-receive common amplifier used in a communication apparatus.
2. Description of Related Art
As car telephone systems have come into commercial operation in various parts of the world, mobile communications have been attracting attention for their future potential. Mobile communications cover a very wide range of fields, including car telephones, business-use radio communications, personal radio communications, and many other fields of applications. These fields have been developing recently at a rapid pace, and in any of these fields, efforts are being made to reduce the size, weight, and power consumption of mobile units for increased convenience of portability.
To achieve this, much of the efforts are focused on making the amplifiers and mixers used in the radio sections of mobile units, as well as components of the baseband sections, smaller and lighter by designing them in integrated circuit form, and vigorous development is also under way to reduce the size of passive components such as filters.
However, simply improving these component parts is not enough to achieve a drastic reduction in the size of the mobile unit itself. As disclosed in IEEE 1993 MICROWAVE AND MILLIMETER-WAVE MONOLITHIC CIRCUITS SYMPOSIUM, pp. 23-26, for example, a reduction in circuit size is achieved by designing a common mixer that can be used for both transmission and reception.
There has also been developed a transistor known as two-mode channel transistor TMT, which is currently under application for a U.S. patent (U.S. Ser. No. 8/109,354) by the applicant of this invention; with only one transistor of this type, transmission and reception can be served satisfactorily and the circuitry can be reduced in size without sacrificing circuit performance. The TMT has two electron flow modes: when the gate bias is deep, electrons flow primarily through an undoped semiconductive layer, and when the gate bias is shallow, electrons flow primarily through a highly doped layer. When the gate bias is deep, electrons tend to flow through regions formed away from impurity doped regions and are therefore less affected by impurities; this serves to further suppress noise generation, providing ultra low noise characteristic. On the other hand, when the gate bias is shallow, a high output characteristic is achieved.
In the case of FETs including the TMT, a deep gate bias means that the voltage to be applied to the gate is small and a shallow gate bias means that. the voltage to be applied to the gate is large. For example, when the deep gate bias is -3 V, the shallow gate bias is -1 V large than -3 V.
FIG. 1 is a block diagram showing an RF (radio frequency) radio section when a TDMA-TDD (time division multiple access--time division duplex) communication system is employed. An RF signal received at an antenna 1 is passed through a transmit-receive common band-pass filter (BPF) 41, and inputted to reception amplifiers 21 and 22 via a transmit-receive common selector switch 4 with a selector terminal 4a connected to a common terminal 4c. The received signal is further passed through a BPF 42 and fed, via a selector terminal 6a and a common terminal 6c in a switch 6, into a mixer 10 where it is mixed with an output from a local oscillator 9 supplied via a buffer amplifier 8. After being down-converted into an intermediate frequency (IF) signal in the mixer 10, the signal is supplied via a switch 7, with a selector terminal 7b connected to a common terminal 7c, to a receiving system circuit for demodulation.
Turning now to the transmitting system, a transmitted signal modulated at the IF band is fed into the mixer 10 via the switch 6 with its selector terminal 6b connected to the common terminal 6c, while at the same time, an output, from the local oscillator 9 is fed into the mixer 10 via the buffer amplifier 8. The IF transmitted signal is up-converted in the mixer 10 into an RF signal. The RF signal is then directed by the switch 7, with its selector terminal 7a connected to the common terminal 7c, is passed through a BPF 43, and is fed into transmission amplifiers 31 and 32 where the signal is amplified to a level that satisfies the specification of the communication apparatus. The amplified signal is then directed by the switch 4 with its selector terminal 4b connected to the common terminal 4c, is passed through the transmit-receive common BPF 41, and is outputted to the antenna 1 from which the radio wave is radiated.
FIGS. 2 and 3 illustrate the block diagram of FIG. 1 in detailed circuit diagram form, FIG. 2 for reception and FIG. 3 for transmission. Bias voltages are also shown in these circuit diagrams.
The switch 4 consists of FETs 51, 52 and resistors 81, 82 connected to the gates of the respective FETs 51, 52. The gates of the FETs 51, 52 are respectively connected to voltage sources (voltage V.sub.ctl1, voltage V.sub.ct12) via the respective resistors 81, 82.
The reception amplifiers 21, 22 together consist of a reception amplifier input matching circuit 101, a reception amplifier output matching circuit 102, FETs 53 and 54, a blocking capacitor 77, and inductors 71, 72 and resistors 83, 84 for bias application. The drain of the FET 53 whose gate is connected to the reception amplifier input matching circuit 101 is connected to a voltage source (voltage V.sub.DD1) via the inductor 71; the gate of the FET 53 is also connected to a voltage source (voltage V.sub.GG1) via the resistor 83. The blocking capacitor 77 is interposed between the drain of the FET 53 and the gate of the FET 54. The gate of the FET 54 whose drain is connected to the reception amplifier output matching circuit 102 is connected to the voltage source (voltage V.sub.GG1) via the resistor 84; the drain of the FET 54 is also connected to the voltage source (voltage V.sub.DD1) via the inductor 72. The sources of the FETs 53 and 54 are grounded.
The transmission amplifiers 31, 32 together consist of a transmission amplifier input matching circuit, 104, a transmission amplifier output matching circuit 103, FETs 55 and 56, a blocking capacitor 78, and inductors 73, 74 and resistors 85, 86 for bias application. The drain of the FET 56 whose gate is connected to the transmission amplifier input matching circuit 104 is connected to a voltage source (voltage V.sub.DD2) via the inductor 74; the gate of the FET 56 is also connected to a voltage source (voltage V.sub.GG2) via the resistor 86. The blocking capacitor 78 is interposed between the drain of the FET 56 and the gate of the FET 55. The gate of the FET 55 whose drain is connected to the transmission amplifier output matching circuit 103 is connected to the voltage source (voltage V.sub.GG2) via the resistor 85; the drain of the FET 55 is also connected to the voltage source (voltage V.sub.DD2) via the inductor 73. The sources of the FETs 55 and 56 are grounded.
The switch 6 consists of FETs 57, 58 and resistors 87, 88 connected to the gates of the respective FETs 57, 58. The gates of the FETs 57, 58 are respectively connected to the voltage sources (voltage V.sub.ctl1, voltage V.sub.ctl2) via the respective resistors 87, 88. Also, the switch 7 consistsof FETs 59, 60 and resistors 89, 90 connected to the gates of the respective FETs 59, 60. The gates of the FETs 59, 60 are respectively connected to the voltage sources (voltage V.sub.ctl2, voltage V.sub.ctl1) via the respective resistors 89, 90.
The mixer 10 consists of a mixer input matching circuit 105, a mixer output matching circuit 106, a dual-gate FET 61, and an inductor 75 and resistor 91 for bias application. The first gate of the dual-gate FET 61 is connected to a voltage source (voltage V.sub.GG3) via the resistor 91, while the drain of the FET 61 is connected to a voltage source (voltage V.sub.DD) via the inductor 75. Further, the first gate, the second gate, and the drain of the dual-gate FET 61 are connected to the mixer input matching circuit 105, a local oscillator input matching circuit 107 described below, and the mixer output matching circuit 106, respectively. The source of the dual-gate FET 61 is grounded.
The buffer amplifier 8 consists of the local oscillator input matching circuit 107, an FET 62, and an inductor 76 and resistor 92 for bias application. The drain of the FET 62 whose gate is connected to the local oscillator 9 is connected to the voltage source (voltage V.sub.DD) via the inductor 76; the gate of the FET 62 is also connected to the voltage source (voltage V.sub.GG3) via the resistor 92. The drain of the FET 62 is also connected to the local oscillator input matching circuit 107, while the source of the FET 62 is grounded.
Further, an IF input matching circuit, 108 is provided in the rear-end stage of the transmitting system circuit, and an IF output matching circuit 109 in the front-end stage of the receiving system circuit.
Next, the operation of the above-configured circuit will be described. First, in reception, V.sub.ctl1 for each of the switches 4, 6, 7 is set, for example, to 0 V to turn on the corresponding FET, and V.sub.ctl2 is set, for example, to -3 V to turn off the corresponding FET, as shown in FIG. 2. The bias voltages, V.sub.DD1 and V.sub.GG1, for the reception amplifiers 21, 22 are set at optimum values, i.e., at values that provide low noise characteristics and that minimize current consumption; for example, V.sub.DD1 =3 V and V.sub.GG1 =-0.5 V. For the mixer 10, the drain bias is fixed to a predetermined value (for example, always ON with V.sub.DD =3 V), and the gate bias is set deep (for example, V.sub.GG3 =-2 V) to reduce the current consumption. During reception, since the transmission amplifiers 31 and 32 are not used, the FETs 55 and 56 are each set in the pinch-off condition (V.sub.DD2 =0 V, V.sub.GG2 =-3 V) to prevent system noise, etc. from leaking outside the system.
Under such bias conditions, the received signal is first passed through the FET 51 in the ON state in the switch 4 that separates reception and transmission, and is then inputted to the reception amplifiers 21, 22. Usually, the reception amplifier input matching circuit 101 is designed to minimize the noise figure of the amplifier, and the reception amplifier output matching circuit 102 is adjusted to achieve the gain matching. The received RF signal is further passed through the BPF 42 and the FET 57 in the ON state, and fed into the mixer 10 where it is mixed with an output power from the local oscillator 9 for conversion into an IF signal. Since the input/output impedance of the BPF 42 is usually 50 Ohms, the input circuit of the mixer 10 is matched to 50 Ohms at the RF band, and the mixer output matching circuit 106 also is adjusted for matching at the RF band so that the output is fed in optimum conditions into the BPF 43 during the transmitting period hereinafter described. Accordingly, the IF signal outputted from the mixer 10 is passed through the FET 60 in the ON state and matched by the IF output matching circuit 109 before being transferred to the receiving system circuit for demodulation.
On the other hand, in transmission, V.sub.ctl1 is set, for example, to -3 V to turn off the corresponding FET, and V.sub.ctl2 is set, for example, to 0 V to turn on the corresponding FET, as shown in FIG. 3. Since the reception amplifiers 21, 22 are not used, the drain voltage V.sub.DD1 is set at 0 V and the gate bias V.sub.GG1 at -3 V to put the respective FETs in the pinch-off condition. The bias conditions for the transmission amplifiers 31, 32 are so set as to maximize the output, i.e., V.sub.DD2 at 3 V and V.sub.GG2 at -1 V. Further, the gate bias for the mixer 10 is set less deep than during the receiving period, to increase the output as compared to that during the receiving period. More specifically, V.sub.DD remains at 3 V, but V.sub.GG3 is set at -1 V.
Under such bias conditions, a digital-modulated signal is inputted from the transmitting system circuit to the mixer 10 via the IF input matching circuit 108 and via the FET 58 in the ON state. In the mixer 10, the signal is t mixed with an output signal from the local oscillator 9 for up-conversion. Since the mixer input matching circuit 105 is adjusted for matching at the RF band, as earlier described, the IF input matching circuit 108 is provided to ensure that the IF signal in the IF band is properly inputted to the mixer 10. Furthermore, the gate bias V.sub.GG3 for the buffer amplifier 8 and the dual-gate FET 61 in the mixer 10 is set less deep than during the receiving period, so that the output power of the local oscillator 9 to be fed into the mixer 10 is increased, and hence a large output power is obtained from the dual-gate FET 61. The mixer output matching circuit 106 of the mixer 10 is matched to 50 Ohms, and the output signal is inputted to the transmission amplifiers 31, 32 via the FET 59 in the ON state and via the BPF 43. The transmission amplifiers 31, 32 amplify the input signal to an output level that satisfies the specification of the communication apparatus, and the amplified RF signal is outputted via the FET 52 in the ON state.
In the case of mobile communications, a very large dynamic range of the reception level poses a problem with the above-described circuit configuration. For example, in a car telephone system, a dynamic range of 70 dB or more is required. When the mobile unit is far away from the base station and the reception level is low, for example, there will be no problem, but when the reception level is high, the amplifiers and mixer used in the mobile unit may be saturated and the signal may not be demodulated properly. In general, the reception amplifier 22 is designed as a variable-gain type, as shown in FIG. 1, to solve this problem. More specifically, the gain is varied by controlling the gate bias V.sub.GG1. While this method can vary the gain, the problem is increased distortion occurring when the gain is reduced. Another possible method will be to control the level by providing a variable attenuator on the input side of the received signal. This method, however, has the problem that the noise figure is increased.
Furthermore, in the above prior art configuration, the voltage switching between transmission and reception involves changing not only the voltages applied to the switches but the biases applied to the amplifiers. This requires a very complex circuit configuration, and it is extremely difficult to integrate the circuit. Moreover, the circuit requires the provision in duplicate of the amplifiers, BPFs, etc. respectively having the same basic function, and such a circuit design is not appropriate for mobile communications terminals for which smaller size and lighter weight are greatly demanded.